The cost of testing an integrated circuit (IC) during manufacture is proportional to the length of the tests used. That is, the cost is proportional to the number of tester cycles used to apply test patterns to the IC. The length of the test patterns applied to a scan-testable circuit, i.e., an IC in which flip-flops can be arranged into one or more serial scan chains, is a function of the length of those scan chains. For example, the longer the scan chains, the more tester cycles are required to fill them with stimulus data and to unload response data.
One solution used to reduce the length of test patterns is to use shorter scan chains, e.g., the scan chains depicted in FIG. 1. Unfortunately, the use of shorter scan chains results in an increase in the number of scan chains used. This can be problematic because each scan chain typically requires its own data input pins, e.g., SCAN IN0 through SCAN INn, and data output pins, e.g., SCAN OUT0 through SCAN OUTn. Given that ICs have limited numbers of pins, restrictions are placed on the number of scan chains that can be used. Thus, the degree of parallelism of scan chains that can be employed to reduce test costs also is restricted.
A technique for reducing the number of pins used for multiple scan chains involves several of the scan chains sharing a single data input pin. As shown in the example of FIG. 2, scan chains 00 through N0 receive input data from the SCAN IN pin. This configuration provides the same data to flip-flops that occupy the same relative positions. For instance, flip-flops 00, 10 . . . N0 receive the same data. The data outputs of the scan chains also may be compressed, such as by using a multiple input signal register (MISR). The above technique is known in the literature as the “Illinois scan” technique.
As noted above, the sharing of scan input data among multiple scan chains results in the “nth” flip-flop of each of the parallel scan chains having the same data bit. This can impose undue restrictions on the variety of data patterns that can be loaded into the IC and may reduce fault coverage.